Why Microsoft’s Partnership with Cisco Silicon One P200 Could Rewrite the Rules of Network Powerplay—And What It Means for Your Bottom Line
Ever wonder what powers the behind-the-scenes data highway of AI—the supercharged express route zipping massive info parcels between data centers? Turns out, Microsoft’s just put Cisco’s Silicon One P200 routing chip to work, and it’s tackling this unglamorous yet crucial task like a champ. Unveiled mere months ago in October 2025, this beast is already humming inside one of the world’s largest cloud networks, signaling that industry giants aren’t waiting around for tomorrow’s tech—they’re grabbing it today. This chip’s not just moving data; it’s redefining speed and efficiency with a single unit that replaces 92 older chips and slashes power use by 65%. If that doesn’t make you stop and rethink how the backbone of AI infrastructure evolves, what will? Dive in as we unpack why this collaboration between Microsoft and Cisco could be a game changer for the AI data traffic puzzles we all still wrestle with. LEARN MORE
Microsoft has started using systems powered by Cisco’s Silicon One P200, a routing chip built for one of the least glamorous and most important jobs in AI: moving huge volumes of data between data centers.
The chip was only unveiled on October 8, 2025. Seeing it running inside one of the world’s largest cloud networks this soon suggests the hyperscalers were not waiting around.
What the P200 actually does
Cisco calls it a deep-buffer routing processor. A buffer is a holding area where data waits briefly when traffic spikes. A deeper buffer means fewer dropped packets when everything arrives at once.
That matters because AI traffic is not polite. Training and inference jobs tend to send data in bursts, and networks built for steadier workloads can choke on them.
Cisco launched the P200 alongside its 8223 routing system. The headline specs:
- 51.2 Tbps of full-duplex throughput
- A compact 3RU form factor, meaning it occupies three standard units of rack space
- 64 × 800G ports on the 8223 system
- Shared buffer technology, programmability and integrated security features
Full-duplex means data flows in both directions at once. So the 51.2 Tbps figure covers traffic going out and coming back at the same time.
Ninety-two chips become one
According to Cisco, a single P200 does the processing work that previously required 92 earlier-generation chips.
That shrinkage translates into power savings. Cisco says the new setup uses 65% less power than its previous 8804 system while delivering the same routing capacity.
Cisco is also pitching the P200 for what it calls “scale-across” architectures. In multi-layer topologies, the company says these designs could potentially reach up to 3 exabits per second.
Microsoft as an early believer
Microsoft is not a newcomer to Silicon One. It has been an early adopter of the chip family and uses the architecture across several parts of its Azure networking stack.
Those roles include data center networking, wide area networking (the long-haul links connecting facilities) and AI and machine learning applications.
Dave Maltz of Microsoft has stressed that networks need to get faster to handle the data bursts generated by AI workloads. He has also affirmed the company’s early commitment to Silicon One.
Microsoft is not the only hyperscaler in line. Following the announcement, P200-powered systems began shipping to major cloud customers including Microsoft Azure and Alibaba.
On the software side, Cisco is trying to appeal to two camps. The P200 initially supports SONiC, an open-source network operating system popular with large cloud operators, with plans to expand support to Cisco’s own IOS XR.
What this means
There are open questions. The 3 exabits per second figure describes a potential ceiling in multi-layer designs, not a demonstrated deployment. And IOS XR support remains a plan, not a shipping feature, which may matter to enterprise customers who are not running SONiC.
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